The Agilent / Keysight N4903A J-BERT is a high-performance serial BERT with complete jitter tolerance and is ideal for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. The pattern generator has significantly low jitter and extremely fast transition times producing clean signals that provide accurate characterization and faster test execution.

With the Agilent / Keysight N4903A J-BERT, test set up is made simple because the N4903A is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns. SER/FER analysis allows jitter tolerance testing of devices using retimed loopback. A second data output with independent pattern memory and PRBS can be used as aggressor channel for crosstalk tests, or when adding channels externally for OOB timing tests or emulation of 3-level signals or signal de-emphasis. It provides the most complete jitter tolerance test for embedded and forward clocked devices.

Features and Specifications of:

●Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector. Option to extended data rate to 14.2 Gb/s for pattern generator.

●>0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC

●Arbitrary SSC profile and extended SSC range to characterize SATA/SAS and USB3 receivers under real-world condition

●Excellent signal performance and sensitivity

●Improved output signal performance

●Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture, frame error rate (FER), or symbol error rate (SER) coded and retimed data streams

●Two adjustable data outputs with independent PRBS and pattern with 120 block pattern sequencer

●Variable output levels on trigger and aux data outputs

●All options are retrofittable and upgrade from N4903A possible

●Built-in clock data recovery with tunable and compliant loop bandwidth

●Supports testing of forwarded clock devices:

oHalfrate clock with variable duty cycle

oJitter on clock and data

oDelay of jitter between clock and data

●PCIe 2.0 compliant jitter injection:

oLF-RJ and HF-RJ

odual-tone PJ

oresidual SSC

oelectrical idle

●16x FC testing with extended data rate for the pattern generator up to 14.2 Gb/s

●Wider PJ range up to 300 MHz

●Pattern generator key characteristics:

oAvailable as 7 and 12.5 Gb/s pattern generator without error detector (Options G07 and G13), extension to 14.2Gb/s (Option D14)

oDifferential outputs with variable output levels for data, aux data, clock and trigger

oLowest intrinsic jitter – 800 fs rms

oTransitions times < 20 ps

oHalf-rate clock with variable duty cycle (Option 003)

oPattern sequencer with up to 120 blocks and counted loops

oSecond output channel (Option 002)

oCalibrated and integrated jitter injection with SJ, two-tone PJ, RJ/sRJ, BUJ, ISI, S.I. (Option J10, J20)

oSSC and residual SSC (Option J11)

oAutomated jitter tolerance characterization sweep makes use of SJ and PJ using 610 ps or 220 ps delay line

oHigh precision delay control input to inject jitter from an external source

oElectrical idle state on data outputs

●Error detector key characteristics:

oTrue differential inputs to match today’s ports

oBuilt-in CDR with tunable loop-bandwidth up to 12 MHz

oAuto-alignment of sampling point

oBit recovery mode for unknown data traffic (Option AO1)

oSER/FER analysis of coded and retimed data (Option A02)

oBurst mode for testing recirculating loop

oBER result and measurement suite

oQuick eye diagram and mask with BER contours